This invention pertains generally to digital computers and in particular to a direct memory address (DMA) system for linking peripheral devices to such a computer.
As is known, a digital computer may be equipped with a DMA capability to allow various types of input/output devices (I/O devices) to be connected, usually over a shared memory bus. Unfortunately, the use of a shared memory bus requires that the operation of the central processing unit (CPU) of the computer be temporarily halted whenever data is to be passed to (or from) an I/O module. Obviously, if there are many I/O modules connected in the system, the frequency of these interruptions may be so great that the efficiency of the system is degraded to an unacceptable degree.
It is known that I/O devices may be connected to a computer system through arrangements including a buffer memory. For example, as shown and described, a magnetic drum is arranged so as to be accessible independently to the CPU of a computer system and to a selected one of a plurality of I/O devices. While such an arrangement is useful in many "low speed" applications in which interruption of the CPU are of little moment, the time required to access any given address is too long to allow use in "high speed" applications in which the frequency and duration of CPU interruption must be reduced to a minimum.